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- 1 - k9gbg08u0a k9lcg08u1a K9HDG08U5A rev.1.0, may. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2009 samsung electronics co., ltd. all rights reserved. 32gb a-die nand flash multi-level-cell (2bit/cell) datasheet www..net
- 2 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 revision history revision no. history draft date remark editor 0.0 1. initial issue nov. 12, 2009 draft s.m.lee 0.1 1. value of random read is changed. 2. package size is amended. (14x18 -> 13x18) 3. package configuration for k9hdg08u 5a-l and k9pfg08u5a-l is amended. 4. pin descriptions for vccq and vssq are added. 5. voltage on any pin relative to v ss for vccq=1.8v is added in table 2.1. 6. temperature under bias(t bias ) is deleted. 7. table 2.3 dc and operating characteristics is modified. (vccq=1.8v added) 8. frequency condition of capacitanc e is changed from 1.0mhz to 100mhz. 9. dummy busy time for intelli gent copy-back read(tcbsy2) is added. 10. dummy busy time for intelligent copy-back program(tdcbsyr2) is added. 11. max. value of cache busy in r ead cache(tdcbsyr) is changed from 400us to 90us. 12. re pulse width(trp) is changed from 15ns to 12ns. 13. read cycle time is changed from 30ns to 25ns. 14. re access time(trea) is changed from 25ns to 20ns. 15. ce access time(tcea) is changed from 35ns to 25ns. 16. we high to re low for random data out(twhr2) is changed from 300ns to 180ns. 17. set feature command(efh) is added. 18. get feature command(eeh) is added. nov. 25, 2009 draft s.m.lee 0.2 1. product list is amended. 2. vccq=1.8v is deleted. 3. part id of 52-lga is fixed from k8xxg08uxa-lcb0/lib0 to k8xxg08uxa-mcb0/ mib0. 4. package thickness of k9hdb08u5a is fixed from 0.65mm to 0.75mm. 5. description for interleav ing operation is deleted. 6. f2h command is deleted. 7. meaning is swapped between tcbsy2 and tdcbsyr2. 8. tcwaw is added. 9. value of twhr2 is changed from 180ns to 300ns. 10. tfeat is added. 11. additional res iction of addressing for pr ogram operation is described. dec. 12, 2009 draft s.m.lee 0.3 1. description of tww is amended. 2. the value of tcbsy2 is changed from 5ms to 500us. 3. the value of tdcbsyr2 is changed from 500us to 5ms. 4. two-plane copy-back program command is fixed. 5. description of status read for intelligent copy-back program is added. dec. 29, 2009 draft h.k.kim 1.0 1. pin configuration of 48 tsop is added. 2. 4.26 00h address id cycle is added. 3. 4.27 40h address id cycle is added. 4. 40h address id definition table is added. 5. tcwaw at the register read out model is added. 6. random read time(tr) is changed from 80 s to 250 s. 7. output driver strength iimpedance values are added. may. 25, 2010 final y.e.yoon the attached data sheets are prepared and approved by samsung elec tronics. samsung electronics co., ltd. reserve the right to change the spec- ifications. samsung electronics will eval uate and reply to your requests and questions about device. if you have any questions, please contact the sam- sung branch office near your office. www..net
- 3 - table of contents datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 1.0 introduction ............................................................................................................................... .................................. 5 1.1 product list ............................................................... ............................................................... ........................5 1.2 features ............................................................... ............................................................... ............................5 1.3 general description....................................................................................................... ......................................... 5 1.4 pin configuration (52lga) ................................................................................................. .................................... 6 1.4.1 package dimensions ...................................................................................................... ................................. 6 1.5 package configuration (52lga )............................................................................................. ................................ 7 1.5.1 package dimensions ...................................................................................................... ................................. 7 1.6 package configuration (52lga )............................................................................................. ................................ 8 1.6.1 package dimensions ...................................................................................................... ................................. 8 1.7 pin configuration (48tsop, mono)........................................................................................... .............................. 9 1.7.1 package dimensions ....................................................................................................... ................................. 9 1.8 pin configuration (48tsop, ddp) ............................................................................................ .............................. 10 1.8.1 package dimensions ....................................................................................................... ................................. 10 1.9 pin configuration (48tsop, qdp) ............................................................................................ .............................. 11 1.9.1 package dimensions ....................................................................................................... ................................. 11 1.10 pin description .......................................................................................................... ........................................... 12 2.0 product introduction............ .............. .............. .............. .............. ........... ........... ............ ............................... 15 2.1 absolute maximum ratings ............................................................... ............................................................... 16 2.2 recommended operating conditions ................. ......................................................................... .......................... 16 2.3 dc and operating characteristics( recommended operating conditions other wise noted.) .................................. 16 2.4 valid block............................................................................................................... ............................................... 17 2.5 ac test condition ......................................................................................................... ......................................... 17 2.6 capacitance(ta=25c, vcc=3.3v, f=100mhz) .................................................................................. ................... 17 2.7 mode selection............................................................................................................ ........................................... 18 2.8 program/erase characteristics ............................................................... ..........................................................18 2.9 ac timing characteristics for command / address / da ta input ............. .............. .............. ........... .......... ............. 19 2.10 ac characteristics for operation.................. ....................................................................... ................................. 19 3.0 nand flash technical notes ... ............................................................................................. .................................... 20 3.1 initial invalid block(s)............................. ..................................................................... ............................................ 20 3.2 identifying initial invalid block(s) ...................................................................................... ...................................... 20 3.3 error in write or read operation .......................................................................................... ..................................... 21 3.4 addressing for program operation ..................... ..................................................................... ................................ 23 3.5 system interface using ce don?t-care. ............. ........................................................................ ............................. 25 4.0 timing diagrams ........................................................................................................... ....................................... 26 4.1 command latch cycle ....................................................................................................... .................................... 26 4.2 address latch cycle....................................................................................................... ........................................ 26 4.3 input data latch cycle .................................................................................................... ....................................... 27 4.4 * serial access cycle after read(cle=l, we=h, al e=l)...................................................................... ............... 27 4.5 serial access cycle after read(edo type, cle=l, we =h, ale=l) ...... .............. .............. .............. .............. ...... 28 4.6 status read cycle ......................................................................................................... ......................................... 28 4.7 read operation ............................................................................................................ .......................................... 29 4.8 read operation(intercepted by ce) ......................................................................................... .............................. 29 4.9 random data output in a page .............................................................................................. ............................... 30 4.10 cache read operation................................. .................................................................... .................................... 31 4.11 two-plane page read operation with two-plane random data out ........... .............. .............. ........... ........... .... 32 4.12 two-plane cache read operation with two-plane random data out (1/2).... .............. .............. ........... ........... .33 4.13 two-plane cache read operation with two-plane random data out (2/2).... .............. .............. ........... ........... .34 4.14 page program operation................................................................................................... ................................... 34 4.15 page program operation with ra ndom data input ............ .............. .............. .............. ........... ........... .................. 35 4.16 copy-back program operation with random data in put ....................................................................... .............. 36 4.17 intelligent copy-back program(1 /2) ....................................................................................... .............................. 37 4.18 cache program operation(avail able only within a block) ................. .................................................. .................. 39 4.19 two-plane copy-back program ......................... ...................................................................... ............................. 40 4.20 two-plane intelligent copy-back program(1/3) ....... ....................................................................... ...................... 41 4.21 two-plane page program operation .......................................................................................... .......................... 44 4.22 two-plane cache program operat ion ............. .............. .............. .............. ............ ........... ......... ......................... 45 4.23 block erase operation.................................................................................................... ...................................... 46 4.24 two-plane block erase operatio n ............... .............. .............. .............. ........... ........... ........... ............................. 47 www..net
- 4 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.25 read id operation........................................................................................................ ........................................ 48 4.26 00h address id cycle...................................................................................................... ...................................... 48 4.27 40h address id cycle...................................................................................................... ...................................... 48 4.27.1 id definition table.......... ........................................................................................... ...................................... 49 5.0 device operation .......................................................................................................... ..................................... 51 5.1 page read................................................................................................................. ............................................. 51 5.2 cache read................................................................................................................ ............................................ 52 5.3 two-plane page read............. .............. .............. .............. .............. ............ ........... ........... ..................................... 54 5.4 two-plane cache read .............. .............. .............. .............. .............. ........... ............ ......... .................................... 55 5.5 page program ............................................................................................................... .......................................... 56 5.6 copy-back program......................................................................................................... ....................................... 57 5.7 intelligent copy-back program . ............................................................................................. .................................. 58 5.8 cache program .............................................................................................................. ......................................... 59 5.9 register read out mode 1.......................... ........................................................................ ................................... 62 5.10 register read out mode 2................................................................................................. .................................. 62 5.11 two-plane register read out mode 1 .............. ......................................................................... .......................... 63 5.12 two-plane register read out mode 2 .............. ......................................................................... .......................... 64 5.13 two-plane page program................................................................................................... .................................. 65 5.14 two-plane copy-back program .............................................................................................. .............................. 66 5.15 two-plane intelligent copy-back program(1/2)..... ......................................................................... ....................... 69 5.16 two-plane cache program.................................................................................................. ................................. 72 5.17 block erase .............................................................................................................. ............................................ 73 5.18 two-plane block erase.................................................................................................... ..................................... 73 5.19 read status.............................................................................................................. ............................................ 74 5.20 read id .................................................................................................................. ............................................... 75 5.21 reset .................................................................................................................... ................................................ 75 5.22 output driver setting ............................... ..................................................................... ......................................... 76 5.23 ready/busy................................................................................................................ ............................................ 78 5.24 00h address id cycle...................................................................................................... ...................................... 79 5.25 40h address id cycle...................................................................................................... ...................................... 79 5.26 device identification table read operation ................................................................................ .......................... 79 6.0 data protection & power up sequence....................................................................................... ............. 81 6.1 wp ac timing guide ........................................................................................................ ...................................... 82 www..net
- 5 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 1.0 introduction 1.1 product list 1.2 features 1.3 general description the device is offered in 3.3v vcc. its nand cell provides the most cost-effective solution for the solid state mass storage ma rket. a program operation can be performed in typical 1.3ms on the 8,832-byte page and an erase operation can be performed in typical 1.5ms on a (1m+80k) byte block. data in the data register can be read out at read cycle time(trc) per by te. the i/o pins serve as the ports for address and data input/ output as well as command input. the on-chip write controller automates all program and er ase functions including pulse r epetition, where required, and i nternal verification and mar- gining of data. even the write-intensive systems can take advantage of the k9xxg08xxa s extended reliability of p/e cycles which are presented in the qualification report by providi ng ecc(error correcting code) with real time ma pping-out algorithm. these nand devices are an op timum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatilit y. part number density interface vccq range vcc range organization pkg type k9gbg08u0a-m 32gb conventional 2.7v ~ 3.6v 2.7v ~ 3.6v x8 52lga 48tsop k9lcg08u1a-m 64gb K9HDG08U5A-m 128gb ? voltage supply - core voltage : 3.3v(2.7v ~ 3.6v) - i/o voltage : 3.3v(2.7v~ 3.6v) ? organization of single die - memory cell array : 8,832 x 519k x 8bit - data register : (8k + 640) x 8bit ? automatic program and erase - page program : (8k + 640)byte - block erase : (1m + 80k)byte ? page read operation - page size : (8k + 640)byte - random read(tr) : 250 s(average typ.), 300 s(average max.) - serial access : 25ns(min.) ? memory cell : 2bit / memory cell ? write cycle time - program time : 1.3ms(typ.) - block erase time : 1.5ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - ecc : 40bit/(1k+80)byte - endurance & data retention : please refer to the qualification report ? command register operation ? unique id for copyright protection ? package : - k9gbg08u0a-mcb0/mib0 : pb/halogen-free package 52-pin lga (13 x 18 / 1.00 mm pitch) - k9lcg08u1a-mcb0/mib0 : pb/halogen-free package 52-pin lga (13 x 18 / 1.00 mm pitch) - K9HDG08U5A-mcb0/mib0 : pb/halogen-free package 52-pin lga (13 x 18 / 1.00 mm pitch) - k9gbg08u0a-scb0/sib : pb/halogen-free package 48-pin tsop (12 x 20 / 1.00 mm pitch) - k9lcg08u0a-scb0/sib0 : pb/halogen-free package 48-pin tsop (12 x 20 / 1.00 mm pitch) - k9hdg08u1a-scb0/sib0 : pb/halogen-free package 48-pin tsop (12 x 20 / 1.00 mm pitch) www..net
- 6 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 1.4 pin configuration (52lga) k9gbg08u0a-mcb0/mib0 1.4.1 package dimensions ab c d e f g h j k l m n nc nc nc nc vssq nc nc nc nc nc nc nc vccq vccq nc nc vcc vcc vss vss vssq /re nc /ce nc cle nc ale nc /we nc /wp nc r/b nc vss io0 nc io1 nc io2 io3 nc nc io4 nc io5 nc io6 nc io7 nc 7 6 5 4 3 2 1 8 0 oa ob oc od oe of 8 7 6 5 4 3 2 1 0 13.00 0.10 #a1 18.00 0.10 18.00 0.10 b a 13.00 0.10 (datum b) (datum a) 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 0.10 c 18.00 0.10 top view bottom view 52-lga (measured in millimeters) ? ab c m 0.1 ? ab c m 0.1 0.65 ( max .) 2.00 x 5 = 10.00 2.00 x 3 = 6.00 1.00 2.00 2.00 x 6 = 12.00 2.00 x 4 + 5.00 = 13.00 1.00 5.00 4.475 2.50 2.00 6.50 www..net
- 7 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 1.5 package configuration (52lga) 1.5.1 package dimensions ab c d e f g h j k l m n 7 6 5 4 3 2 1 nc nc nc nc nc nc nc nc nc vccq vccq vcc vcc vss vss vssq /re1 /re2 /ce1 /ce2 cle1 cle2 ale1 ale2 /we1 /we2 /wp1 /wp2 r/b1 r/b2 vss io0-1 io0-2 io1-1 io1-2 io2-1 io3-1 io2-2 io3-2 io4-1 io4-2 io5-1 io5-2 io6-1 io6-2 io7-1 io7-2 vssq k9lcg08u1a-mcb0/mib0 nc nc nc nc 8 0 oa ob oc od oe of 8 7 6 5 4 3 2 1 0 13.00 0.10 #a1 18.00 0.10 18.00 0.10 b a 13.00 0.10 (datum b) (datum a) 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 0.10 c 18.00 0.10 top view bottom view 52-lga (measured in millimeters) ? ab c m 0.1 ? ab c m 0.1 0.65 ( max .) 2.00 x 5 = 10.00 2.00 x 3 = 6.00 1.00 2.00 2.00 x 6 = 12.00 2.00 x 4 + 5.00 = 13.00 1.00 5.00 4.475 2.50 2.00 6.50 www..net
- 8 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 1.6 package configuration (52lga) 1.6.1 package dimensions K9HDG08U5A-mcb0/mib0 ab c d e f g h j k l m n nc nc nc nc nc nc nc nc nc vccq vccq /ce2-1 r/b2-1 vcc vcc vss vss vssq /re1 /re2 /ce1-1 /ce1-2 cle1 cle2 ale1 ale2 /we1 /we2 /wp1 /wp2 r/b1-1 r/b1-2 vss io0-1 io0-2 io1-1 io1-2 io2-1 io3-1 io2-2 io3-2 io4-1 io4-2 io5-1 io5-2 io6-1 io6-2 io7-1 io7-2 vssq r/b2-2 /ce2-2 7 6 5 4 3 2 1 8 0 oa ob oc od oe of 8 7 6 5 4 3 2 1 0 13.00 0.10 #a1 18.00 0.10 18.00 0.10 b a 13.00 0.10 (datum b) (datum a) 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 0.10 c 18.00 0.10 top view bottom view 52-lga (measured in millimeters) ? ab c m 0.1 ? ab c m 0.1 0.75 ( max .) 2.00 x 5 = 10.00 2.00 x 3 = 6.00 1.00 2.00 2.00 x 6 = 12.00 2.00 x 4 + 5.00 = 13.00 1.00 5.00 4.475 2.50 2.00 6.50 www..net
- 9 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 1.7 pin configuration (48tsop, mono) 1.7.1 package dimensions 48-pin lead free plastic thin sm all out-line package type(i) 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vcc vss n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c vss vcc vss n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c vcc vss n.c vccq n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c vss vccq k9gbg08u0a-scb0/sib0 48 - tsop1 - 1220af unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 0.20 +0.07 -0.03 www..net
- 10 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 1.8 pin configuration (48tsop, ddp) 1.8.1 package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vcc vss n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c vss vcc vss n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c vcc vss n.c vccq n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c vss vccq k9lbg08u0a-scb0/sib0 48 - tsop1 - 1220af unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 0.20 +0.07 -0.03 www..net
- 11 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 1.9 pin configuration (48tsop, qdp) 1.9.1 package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vcc vss n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c vss vcc vss n.c n.cn. c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c vccq vcc vss n.c vccq n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c vss k9hbg08u1a-scb0/sib0 48 - tsop1 - 1220bf unit :mm #1 #24 0.50typ [0.50 0.06] #48 0.10 0.075 max 0.02 min (18.80) ( 1 3 ) 0.125 +0.075 -0.035 0.20 +0.07 -0.03 (1.00) (1.00) (1.00) (1.00) #25 (0.25) 18.40 . 0.10 (19.00) 20.00 . 0.20 0.4625 0.15 0.4625 0.15 ( r 0.15) ( r 0.15 ) (10 ) 1.20max 1.0 5. 0.3 (13 ) ( 1 0 ) 12.00 . 0.10 ( r 0 . 1 5 ) ( r 0 .15 ) 0.45 ~ 0.75 (0.50) 0 ~ 8 ( r 0 . 2 5 ) ( r 0 . 2 5 ) 0.25typ 0.16 +0.07 -0.03 ( 0.80 dp 0~0.05) ( 1 . 0 0 d p 0 ~ 0 . 0 5 ) (2- 1.20 dp 0~0.05) www..net
- 12 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 1.10 pin description note : connect all vcc and vss pins of eac h device to common power supply outputs. do not leave either vcc or vss disconnected. the k9gbg08u0a has one ce pins(ce ) and r/b pins(r/b ). the k9lcg08u1a has two ce pins(ce 1 to ce 2) and r/b pins(r/b 1 to r/b 2). the K9HDG08U5A has four ce pins(ce 1-1 to ce 2-2) and r/b pins(r/b 1-1 to r/b 2-2). for k9hdg08x5a, ce 1-1, ce 2-1 and r/b 1-1, r/b 2-1 are mapped to i/o0-1 ~ i/o7-1. ce 1-2, ce 2-2 and r/b 1-2, r/b 2-2 are mapped to i/o0-2 ~ i/o7-2. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands s ent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the acti vating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. re read enable the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the fall- ing edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent program/era se protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when lo w, it indicates that a program, erase or random read oper- ation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z conditio n when the chip is deselected or when outputs are disabled. vcc power v cc is the power supply for device. vccq i/o power the vccq is the power supply for input and/or output signals. vss ground vssq i/o ground the vssq is the power supply ground n.c no connection lead is not internally connected. www..net
- 13 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 functional block diagram array organization of single die note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. * row address consists of page address (a 14 ~ a 20 ) & plane address(a 21 ) & block address(a 22 ~ the last address) i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 a 12 a 13 *l *l 3rd cycle a 14 a 15 a 16 a 17 a 18 a 19 a 20 a 21 4th cycle a 22 a 23 a 24 a 25 a 26 a 27 a 28 a 29 5th cycle a 30 a 31 a 32 a 33 *l *l *l *l v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 14 - a 33 a 0 - a 13 command ce re we cle wp i/0 0 i/0 7 v cc v ss ale nand flash array y-gating data register & s/a r/b 8k bytes 640 bytes 531,456 pages (=4,152 blocks) 8k bytes 8 bit 640 bytes 1 block = 128 pages (1m+ 80k) bytes i/o 0 ~ i/o 7 1 page = (8k + 640)bytes 1 block = (8k + 640)b x 128 pages = (1m +80k) bytes 1 device = (8k + 640)b x 128 pages x 4,152 blocks = 36,670,464 kbits page register row address; column address plane address : a 21 block address : a 22 ~ a 33 page address : a 14 ~ a 20 www..net
- 14 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 spare blocks arrangement the device has 56 spare blocks to incr ease valid blocks. extended blocks can be accessed by the following address. block 0 block 1 block 2 block 3 block 4 block 5 ? ? ? block 4094 block 4095 block 4096 block 4097 ? ? ? block 4150 block 4151 page address (hexadecimal) 00000h 00080h 00100h 00180h 00200h 00280h 7ff00h 80000h main blocks (4096 blocks) extended blocks (56 blocks) 7ff80h 80080h 81b00h 81b80h www..net
- 15 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 2.0 product introduction nand flash memory has addresses multiplexed into 8 i/os. this scheme dramatically reduces pin counts and allows system upgrades to future densiti es by maintaining consistency in system board design. command, address and data are all writt en through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. some commands require one bus cycle. for example, reset command, status read command, etc. requ ire just one cycle bus. some other commands, like page read and block erase and p age program, require two cycles: one cycle for setup and the othe r cycle for execution.. page read and page program need the same five address cycles following the required co mmand input. in block erase operation, ho wever, only the three row address cycles are used. device operations are selected by writing specific commands in to the command register. the t able below defines the specific commands of the k9xxg08uxa. command sets note : 1) random data input/output can be executed in a page. 2) any command between 11h and 80h/81h/85h is prohibited except 70h/f1h and ffh. 3) two-plane random data out must be used after two-plane read or two-plane cache read operation caution : any undefined command inputs are prohibited except for above command set. function 1st set 2nd set acceptable command during busy read 00h 30h read for copy-back 00h 35h intelligent copy-back read 00h 3ah cache read 31h - read start for last page cache read 3fh - page program 80h 10h cache program 80h 15h copy-back program 85h 10h intelligent copy-back program 8ch 15h block erase 60h d0h random data input (1) 85h - random data output (1) 05h e0h two-plane read (3) 60h----60h 30h two-plane read for copy-back (3) 60h----60h 35h two-plane intelligent copy-back read 60h----60h 3ah two-plane random data output (1) (3) 00h----05h e0h two-plane cache read (3) 60h----60h 33h two-plane page program (2) 80h----11h 81h----10h two-plane copy-back program (2) 85h----11h 81h----10h two-plane intelligent copy-back program 8ch----11h 8ch----15h two-plane cache program (2) 80h----11h 81h----15h two-plane block erase 60h----60h d0h read id 90h - read status 70h - o read status1 f1h - o set feature efh - get feature eeh - reset ffh - o www..net
- 16 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 2.1 absolute maximum ratings note : 1) minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is vcc+0.3v which, during transitions, may overshoot to vcc+2.0v for periods <20ns. 2) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data shee t. exposure to absolute maximum ra ting conditions for extended per iods may affect reliability. 2.2 recommended operating conditions (voltage reference to gnd, k9xxg08uxa-xcb0 : t a =0 to 70 c (1) , k9xxg08uxa-xib :vt a =-40 to 85 c (1) ) note: 1) data retention is not guaranteed on the operating condition temperature under/over. 2.3 dc and operating characteristics (recommended operating conditions otherwise noted.) note : 1) the typical value of the k9lcg08u1a?s i sb is 20 a and the maximum value is 100 a. the typical value of the K9HDG08U5A?s i sb is 40 a and the maximum value is 200 a. 2) the maximum value of K9HDG08U5A?s are 20 a. 3) vil can undershoot to -0.4v and vih can overshoo t to vcc +0.4v for durations of 20 ns or less. 4) typical value is measured at vcc=3.3v, ta=25 c. not 100% tested. parameter symbol rating unit voltage on any pin relative to v ss v cc -0.6 to +4.6 v v in vccq=3.3v -0.6 to +4.6 v i/o vccq=3.3v -0.6 to +4.6 storage temperature k9xxg08xxa-xcb0/xib0 t stg -65 to +100 c short circuit current ios 5 ma parameter symbol min typ. max unit supply voltage v cc 2.7 3.3 3.6 v supply voltage v ss 000 i/o voltage vccq(3.3v) 2.7 3.3 3.6 i/o voltage vssq 0 0 0 parameter symbol test conditions vccq=3.3v unit min typ max operating current page read with serial access i cc1 trc=25ns ce =v il, i out =0ma -3050ma program i cc2 - erase i cc3 - stand-by current(cmos) i sb (1) ce =vccq-0.2, wp =0v/vccq - 10 50 a input leakage current i li (2) v in =0 to vccq(max) - - 10 output leakage current i lo (2) v out =0 to vccq(max) - - 10 input high voltage v ih (3) - 0.8 xvccq - vccq +0.3 v input low voltage, all inputs v il (3) - -0.3 - 0.2 xvccq output high voltage level v oh i oh =-400 a2.4-- output low voltage level v ol i ol =2.1ma - - 0.4 output low current(r/b )i ol (r/b )v ol =0.4v 8 10 - ma www..net
- 17 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 2.4 valid block note : 1) the device may include initial invalid blocks when first ship ped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits which cause status f ailure during program and erase operation. do not erase or program factory-marked bad blocks. refer to the at tached technical notes for appropriate management of invalid bl ocks. 2) the 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment 3) the number of valid blocks is on the basis of single pl ane operations, and this may be decreased with two plane operations. * each single die in k9lcg08u1a and K9HDG08U5A has maximum 116 invalid blocks. 2.5 ac test condition (k9xxg08uxa-xcb0 :t a =0 to 70 c, k9xxg08uxa: vcc=2.7v ~ 3.3v,unless otherwise noted) 2.6 capacitance(t a =25 c, v cc =3.3v, f=100mhz) note : 1) capacitance is periodically sampled and not 100% tested. 2) ci/o(w) and cin(w) are tested at wafer level. parameter symbol min typ. max unit k9gbg08u0a n vb 4,036 - 4,152 blocks k9lcg08u1a 8,072 8,304 K9HDG08U5A 16,144 16,608 parameter k9xxg08uxa input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl = 5pf item symbol test condition k9gbg08u0a k9lcg08u1a K9HDG08U5A unit min max min max input/output capacitance c i/o v il =0v - 8 - 13 pf c i/o(w)* v il =0v - 5 - 10 pf input capacitance c in v in =0v - 8 - 13 pf c in(w)* v in =0v - 5 - 10 pf www..net
- 18 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 2.7 mode selection note : 1) x can be vil or vih. 2) wp should be biased to cmos high or cmos low for standby. 2.8 program/erase characteristics note : 1) typical program time is measured at vcc=3.3v, t a =25 c. not 100% tested. 2) typical program time is defined as the time within which mo re than 50% of the whole pages are programmed at 3.3v vcc and 25 c temperature. 3) within a same block, program time(tprog) of page group a is faster than that of page group b. typical tprog is the average p rogram time of the page group a and b. page group a: page 0, 1, 3, 5, 7, 9, 11, ... ,115, 117, 119, 121, 123, 125 page group b: page 2, 4, 6, 8, 10, 12, ... , 118, 120, 122, 124, 126, 127 4) tcbsy and tcbsy2 depend on the timing between internal programming time and data in time. cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) lll hh data input lllh x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by parameter symbol min typ max unit program time tprog - 1.3 5ms dummy busy time for two-plane program tdbsy - 0.5 1 s dummy busy time for cache program tcbsy (4) --5ms dummy busy time for intelligent copy-back program tcbsy2 (4) - - 500 s number of partial program cycles in the same page nop - - 1 cycle block erase time tbers - 1.5 10 ms www..net
- 19 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 2.9 ac timing characteristics for command / address / data input note : 1) the transition of the corresponding c ontrol pins must occur only once while we is held low. 2) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. 2.10 ac characteristics for operation note : 1) if reset command(ffh) is written at ready state, the device goes into busy for maximum 10 s. 2) 90us is applied for the average maximum value. parameter symbol min max unit cle setup time tcls (1) 12 - ns cle hold time tclh 5 - ns ce setup time tcs (1) 20 - ns ce hold time tch 5 - ns we pulse width twp 12 - ns ale setup time tals (1) 12 - ns ale hold time talh 5 - ns data setup time tds (1) 12 - ns data hold time tdh 5 - ns write cycle time twc 25 - ns we high hold time twh 10 - ns address to data loading time tadl (2) 300 - ns parameter symbol min max unit ale to re delay tar 10 - ns cle to re delay tclr 10 - ns command write cycle to address write cycle time for random data input tcwaw 300 - ns ready to re low trr 20 - ns re pulse width trp 12 - ns we high to busy twb - 100 ns wp high/low to we low tww 100 - ns read cycle time trc 25 - ns re access time trea - 20 ns ce access time tcea - 25 ns re high to output hi-z trhz - 100 ns ce high to output hi-z tchz - 30 ns ce high to ale or cle don?t care tcsd 0 - ns re high to output hold trhoh 15 - ns re low to output hold trloh 5- ns re high hold time treh 10 - ns output hi-z to re low tir 0 - ns re high to we low trhw 100 - ns we high to re low twhr 120 - ns we high to re low for random data out twhr2 300 - ns device resetting time(read/program/erase) trst - 10/30/100 (1) s busy time for set feature and get feature tfeat - 1 s cache busy in read cache (following 31h and 3fh) tdcbsyr - 90 (2) s dummy busy time for intelligent copy-back read tdcbsyr2 - 5 ms www..net
- 20 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 3.0 nand flash technical notes 3.1 initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial inva lid block information. devices with initial invalid block(s) h ave the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a sele ct transistor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guarant eed to be a valid block at the time of shipment. 3.2 identifying initial invalid block(s) all device locations are erased(ffh) except locations where the in itial invalid block(s) informat ion is written prior to shippi ng. the initial invalid block(s) status is defined by the 1st byte in the spare area. samsung make s sure that the first or the last page of every initial invali d block has non-ffh data at the column address of 0 or 8,192.the initial invalid block information is also erasable in most cases, and it is impossible to reco ver the information once it has been erased. therefore, the system must be able to recognize t he initial invalid block(s) based on the initial invalid block in formation and create the initial invalid block table via the following sugges ted flow chart. any intentional erasure of the initial invalid block information is prohibited. flow chart to create initial invalid block table. note: 1) no erase operation is allowed to detected bad blocks. no yes read ffh check column 0 or 8192 of the last page block no = 1 end pass pass fail start block no. = block no. + 1 read ffh check column 0 or 8192 of the first page entry bad block 1) fail last block www..net
- 21 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 3.3 error in write or read operation within its life time, additional invalid bl ocks may develop with nand flash memory. refer to the qualification report for the a ctual data. block replacement should be done upon erase or program error. note : users are required to employ randomizer function in the nand controller to meet target endurance of the device. ecc : error correcting code --> rs code or bch code etc. example) 40 bit correction / (1k+80) byte program flow chart failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read up to 40 bit failure verify ecc -> ecc correction start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes : if program operation results in an error, map out the block including the page in error and copy the * target data to another block. www..net
- 22 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 nand flash technical notes (continued) * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program block ?a? by creating an ?i nvalid block? table or other appropriate scheme. erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes write 30h : if erase operation results in an error, map out the failing block and replace it with another block. * block replacement buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 www..net
- 23 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 3.4 addressing for program operation within a block, the pages must be programm ed consecutively from the lsb (least signific ant bit) page of the block to msb (most significant bit) pages of the block. random page address programming is prohibited. in this case, the definition of lsb page is the lsb among the pages t o be programmed. therefore, lsb doesn?t need to be page 0. paired page in ?group a? must has been programmed before page in ?group b? program execution. from the lsb page to msb page data in: data (1) data (128) (1) (2) (3) (32) (128) data register page 0 page 1 page 2 page 31 page 127 e.g.) random page program (prohibition) data in: data (1) data (128) (2) (32) (3) (1) (128) data register page 0 page 1 page 2 page 31 page 127 : : : : www..net
- 24 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 paired page address information note : when program operation is abnormally aborted (e.g. power-down, reset), not only page data under program but also paired page da ta may be damaged. paired page address(1/2) paired page address(2/2) group a group b group a group b 00h 02h 3fh 42h 01h 04h 41h 44h 03h 06h 43h 46h 05h 08h 45h 48h 07h 0ah 47h 4ah 09h 0ch 49h 4ch 0bh 0eh 4bh 4eh 0dh 10h 4dh 50h 0fh 12h 4fh 52h 11h 14h 51h 54h 13h 16h 53h 56h 15h 18h 55h 58h 17h 1ah 57h 5ah 19h 1ch 59h 5ch 1bh 1eh 5bh 5eh 1dh 20h 5dh 60h 1fh 22h 5fh 62h 21h 24h 61h 64h 23h 26h 63h 66h 25h 28h 65h 68h 27h 2ah 67h 6ah 29h 2ch 69h 6ch 2bh 2eh 6bh 6eh 2dh 30h 6dh 70h 2fh 32h 6fh 72h 31h 34h 71h 74h 33h 36h 73h 76h 35h 38h 75h 78h 37h 3ah 77h 7ah 39h 3ch 79h 7ch 3bh 3eh 7bh 7eh 3dh 40h 7dh 7fh www..net
- 25 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 3.5 system interface using ce dont-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. t he internal 8,832byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. in addition, for voice or audio appli cations which use slow cycle time on the order of -seconds, de-activating ce during the data-loading and serial access would pr ovide significant savings in power consumption. program operation with ce don?t-care read operation with ce don?t-care ce we t wp t ch t cs address(5cycles) 80h data input ce cle ale we data input ce don?t-care 10h t cea out t rea ce re i/o 0 ~ 7 i/ox address(5cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re 30h i/ox www..net
- 26 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.0 timing diagrams 4.1 command latch cycle ce we cle ale command t cls t cs t clh t ch t wp t als t alh t ds t dh i/ox 4.2 address latch cycle ce we cle ale col. add1 t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh t cls www..net
- 27 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.3 input data latch cycle 4.4 * serial access cycle after read (cle=l, we =h, ale=l) note : 1) transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2) trloh is valid when frequency is higher than 20mhz. trhoh starts to be valid when frequency is lower than 20mhz. ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox re ce r/b dout dout dout t rc t rea t rr t rhoh t rea t reh t rea t rhz i/ox t chz t rhz www..net
- 28 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.5 serial access cycle after read (edo type, cle=l, we =h, ale=l) note : 1) transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2) trloh is valid when frequency is higher than 20mhz. trhoh starts to be valid when frequency is lower than 20mhz. 4.6 status read cycle re ce r/b i/ox t rr t cea t rea t rp t reh t rc t rhz t chz t rhoh t rloh dout dout t rea ce we cle re 70h/f1h status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t whr t cea t cls i/ox t chz t rhz t cs www..net
- 29 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.7 read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc | | | row add2 30h t clr i/ox row add3 4.8 read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h i/ox col. add1 col. add2 row add1 row add2 row add3 t clr t csd www..net
- 30 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.9 random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr t r c 30h/35h i/ox col. add1 col. add2 row add1 row add2 row add3 t rhw 05h column address col. add1 dout n+1 05h column address dout m dout m+1 col. add1 col. add2 e0h t rhw t clr t whr2 t rea ce cle r/b we ale re i/ox 1 1 www..net
- 31 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.10 cache read operation note : 1) the column address will be reset to 0 by the 31h and 3fh command input. 2) cache read operation is available only within a block. tdcbsyr trc 31h twb trr d0 d1 page address m+2 col. add. 0 tdcbsyr trc d0ut 31h twb trr d0 d1 page address m+3 col. add. 0 tdcbsyr trc d0ut 3fh twb trr d0 d1 page address m+4 col. add. 0 ce cle r/b we ale re i/ox 1 1 tdcbsyr trc 31h twb trr d0 d1 page address m d0ut 31h twc twb tr 00h 30h col. add. 0 col. add1 col. add2 row add1 row add2 row add3 ce cle r/b we ale re i/ox www..net
- 32 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.11 two-plane page read operati on with two-plane random data out 60h tw row address twc 60h tw row address twc 30h busy t wb t r page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n row add1 row add2 row add3 row add1 row add2 row add3 ce cle r/b we ale re i/ox 1 00h column address tw row address twc column address 05h dout n 1 t rea t whr2 t clr e0h t rc dout n+1 column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 ce cle r/b we ale re i/ox column address : valid 2 dout n 00h column address tw row address twc column address 05h e0h dout m t rea t whr2 t clr t whr2 t clr t rea e0h t rc t rc dout n+1 t rhw dout m+1 column address : fixed ?low? page address page m plane address : fixed ?high? block address : block n column address : valid col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 ce cle r/b we ale re i/ox 2 www..net
- 33 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.12 two-plane cache read operation wi th two-plane random data out (1/2) 60h tw row address twc 60h tw row address twc 33h 1 busy t wb t r page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n row add1 row add2 row add3 row add1 row add2 row add3 ce cle r/b we ale re i/ox 00h column address tw row address twc column address 05h dout n 1 ce cle r/b we ale re i/ox t rea t whr2 t clr e0h t rc dout n+1 column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 31h tdcbsyr twb max. 127 times repeatable 2 00h column address tw row address twc column address 05h e0h dout m t whr2 t clr t rea t rc dout n+1 dout m+1 column address : fixed ?low? page address page m plane address : fixed ?high? block address : block n column address : valid col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 ce cle r/b we ale re i/ox 2 00h column address tw row address twc column address : fixed ?low? page address : page m+n plane address : fixed ?low? block address : block n col. add1 col. add2 row add1 row add2 row add3 3fh tdcbsyr twb 3 max. 127 times repeatable www..net
- 34 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.13 two-plane cache read operation with two-plane random data out (2/2) note : 1) the column address will be reset to 0 by the 3fh command input. 2) cache read operation is available only within a block. 3) make sure to terminate the operation with 3fh command. if the operation is terminated by 31h command, monitor i/o 6 (ready/ busy) by issuing status read command (70h) and make sure the previous page read operation is comple ted. if the page read operation is completed, issue ffh reset bef ore next operation. 4.14 page program operation note : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. column address 05h dout n 00h column address tw row address twc column address 05h e0h dout m t rea t whr2 t clr t whr2 t clr t rea e0h t rc t rc dout n+1 dout m+1 column address : valid column address : fixed ?low? page address page m+n plane address : fixed ?high? block address : block n column address : valid col. add1 col. add2 col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 3 ce cle r/b we ale re i/ox ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 row add3 t adl t whr www..net
- 35 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.15 page program operation with random data input note : 1) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. ce cle r/b we ale re 80h din n din m serial data input command column address row address serial input t wc t wc random data input command column address t cwaw i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 t adl t adl 1 70h i/o 0 10h m program command read status command t prog t wb 85h random data input command column address din j din k serial input col. add1 col. add2 t adl t whr i/o 0 =0 successful program 1 ce cle r/b we ale re i/ox t cwaw 85h www..net
- 36 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.16 copy-back program operation with random data input note : 1) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. 00h 85h row address t wc busy t wb t r copy-back data input command 35h column address row add1 row add2 col. add1 row add3 data 1 data n t rc ce cle r/b we ale re i/ox row address row add1 row add2 row add3 i/o x read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb busy 10h row address data 1 data n col. add2 row add1 row add2 row add3 70h t adl t whr ce cle r/b we ale re i/ox 1 column address col. add1 col. add1 col. add2 col. add2 1 column address www..net
- 37 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.17 intelligent copy-back program(1/2) 00h column address row address t wc busy t wb t r intelligent copy-back read input command 30h col. add1 col. add2 row add1 row add2 row add3 data 1 data n t rc ce cle r/b we ale re i/ox column address row address 3ah col. add1 col. add2 row add1 row add2 row add3 00h data out ce cle r/b we ale re i/ox 8ch t wc busy t wb t cbsy2 15h data 1 data n data 1 data n t rc column address 00h data out column address row address col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 busy t dcbsyr2 1 2 1 00h www..net
- 38 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 intelligent copy-back program(2/2) d a t a 1 c o l u m n a d d r e s s r o w a d d r e s s 3 a h c o l . a d d 1 c o l . a d d 2 r o w a d d 1 r o w a d d 2 r o w a d d 3 t d c b s y r 2 b u s y 2 8 c h t w c b u s y t w b t c b s y 2 1 5 h d a t a 1 d a t a n c o l u m n a d d r e s s r o w a d d r e s s c o l . a d d 1 c o l . a d d 2 r o w a d d 1 r o w a d d 2 r o w a d d 3 3 c e c l e r / b w e a l e r e i / o x data 1 data n t rc data out t wc 10h data 1 data n column address row address col. add1 col. add2 row add1 row add2 row add3 8ch t prog t wb ce cle r/b we ale re i/ox 3 www..net
- 39 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.18 cache program operation (available only within a block) note : 1) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. 2) since programming the last page does not employ caching, the program time has to be that of page program. however, if the pr evious program cycle with the cache data has not finished, the actual program cycle of the last page is initiated onl y after completion of the previous cycle, which can be expressed as the following formula. tprog = program time for the last page + program time for the ( last -1) th page - (command input cycle time + address input cycle time + last page data loading time) maximum tprog is 10ms in this case. e.g.) cache program ce cle r/b we ale re 80h din n din 15h m serial data input command column address serial input program max. 127 times repeatable tcbsy twb twc command last page input & program (dummy) din n 80h row address i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add1 row add2 row add3 row add3 tadl tadl 1 din 10h tprog* 2 twb i/o program confirm command (true) 70h m ce cle r/b we ale re i/ox din n 1 80h col. add1,2 & row add1,2 r/b data address & data input 15h 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h t cbsy t cbsy t cbsy t prog* 2 70h i/ox www..net
- 40 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.19 two-plane copy-back program ce cle r/b we ale re i/ox 60h 35h tr twb 1 00h twc twc row add1 row add2 row add2 col. add1 col. add2 row add1 row add2 row. add3 row address column address row address 60h row add1 row add2 row add2 row address | plane address : fixed ?low? plane address : fixed ?high? 00h col. add1 col. add2 column address column address : fixed ?low? column address : valid e0h dout plane address : fixed ?low? ce cle r/b we ale re i/ox tdbsy twb 1 00h twc col. add1 col. add2 row add1 row add2 row. add3 column address row address 00h col. add1 col. add2 column address column address : fixed ?low? column address : valid e0h dout | | dout | plane address : fixed ?high? 85h twc col. add1 col. add2 row add1 row add2 row. add3 column address row address 11h column address : fixed ?low? plane address : fixed ?low? dout | | dout | 2 tdbsy twb row add2 row. add3 11h tprog twb 81h twc col. add1 col. add2 row add1 row add2 row. add3 column address row address 10h column address : fixed ?low? plane address : fixed ?high? ce cle r/b we ale re i/ox 2 row add1 www..net
- 41 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.20 two-plane intelligent copy-back program(1/3) ce cle r/b we ale re i/ox 60h 30h tr twb 00h twc twc row add1 row add2 row add2 col. add1 col. add2 row add1 row add2 row. add3 row address column address row address 60h row add1 row add2 row add2 row address plane address : fixed ?low? plane address : fixed ?high? 05h col. add1 col. add2 column address column address : fixed ?low? column address : valid plane address : fixed ?low? ce cle r/b we ale re i/ox 00h twc col. add1 col. add2 row add1 row add2 row. add3 column address row address 05h col. add1 col. add2 column address column address : fixed ?low? column address : valid e0h dout dout plane address : fixed ?high? 60h e0h dout dout 1 ce cle r/b we ale re i/ox 8ch twc col. add1 col. add2 row add1 row add2 row. add3 column address row address din din plane address : fixed ?low? 11h tdbsy twb 8ch twc col. add1 col. add2 column address 2 3ah tdcbsyr2 twb 60h row add1 row add2 row add2 row address plane address : fixed ?high? 2 1 3 www..net
- 42 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 two-plane intelligent copy-back program(2/3) twc col. add2 row add1 row add2 row. add3 row address din din plane address : fixed ?high? 15h tcbsy2 twb ce cle r/b we ale re i/ox 4 00h twc col. add1 col. add2 row add1 row add2 row. add3 column address row address 05h col. add1 col. add2 column address column address : fixed ?low? column address : valid e0h plane address : fixed ?low? dout dout 4 00h twc col. add1 col. add2 row add1 row add2 row. add3 column address row address 05h col. add1 col. add2 column address column address : fixed ?low? column address : valid e0h dout dout plane address : fixed ?high? ce cle r/b we ale re i/ox 60h twc row add1 row add2 row add2 row address 60h plane address : fixed ?low? 5 5 3ah tdcbsyr2 twb row add1 row add2 row add2 row address plane address : fixed ?high? 8ch col. add1 col. add2 row add1 row add2 row. add3 column address row address din din plane address : fixed ?low? 11h tdbsy twb ce cle r/b we ale re i/ox 6 8ch twc col. add1 col. add2 row add1 column address plane address : fixed ?high? 3 www..net
- 43 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 two-plane intelligent copy-back program(3/3) row add1 row add2 row. add3 row address din din 7 15h tcbsy2 twb 00h twc col. add1 col. add2 row add1 row add2 row. add3 column address row address 05h col. add1 col. add2 column address column address : fixed ?low? column address : valid e0h dout dout plane address : fixed ?low? ce cle r/b we ale re i/ox 6 ce cle r/b we ale re i/ox 7 00h twc col. add1 col. add2 row add1 row add2 row. add3 column address row address 05h col. add1 col. add2 column address column address : fixed ?low? column address : valid e0h dout dout plane address : fixed ?high? 8ch col. add1 col. add2 row add1 row add2 row. add3 column address row address din din plane address : fixed ?low? 11h 8 ce cle r/b we ale re i/ox 8ch twc col. add1 col. add2 row add1 row add2 row. add3 column address row address din din plane address : fixed ?high? 10h tprog twb 8 11h tdbsy twb www..net
- 44 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.21 two-plane page program operation note : any command between 11h and 81h is prohibited except 70h/f1h and ffh. ce cle r/b we ale re 80h din n din 11h m serial data input command column address program tdbsy twb twc command (dummy) 81h page row address i/ox 1 up to 8,832 byte serial input t dbsy : typ. 500ns max. 1 s col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 row add1 row add2 row add3 data 1 din n 10h i/o program confirm command (true) 70h/f1h din m read status command row add3 twhr i/o 0 =1 error in program i/o 0 =0 successful program twb tprog ce cle r/b we ale re i/ox 1 80h i/o 0 ~ 7 r/b 11h e.g.) two-plane page program t dbsy address & data input 81h 10h address & data input 70h/f1h t prog col. add1,2 & row add 1,2,3 8,832 byte data col. add1,2 & row add 1,2,3 8,832 byte data column address : valid page address : page m plane address : fixed ?low? block address : block n column address : valid page address : page m plane address : fixed ?high? block address : block n note www..net
- 45 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.22 two-plane cache program operation ce cle r/b we ale re i/ox tadl | | | | | | 80h din 0 din 1 11h | | tdbsy twb din 8831 81h din 0 tadl twc twc col. add1 col. add2 row add1 row add2 row add2 col. add1 col. add2 row add1 row add2 row. add3 column address row address column address row address 1 ce cle r/b we ale re i/ox tadl | | | | | | 80h din 0 din 1 11h | | tdbsy twb din 8831 81h twc col. add1 col. add2 row add1 row add2 row add2 column address row address 1 | | | | | | din 0 din 1 15h | | tcbsy twb din 8831 80h col. add1 program command (cache) 2 | | | | | | 81h din 0 din 1 10h | | tprog* twb din 8831 tadl twc col. add1 col. add2 row add1 row add2 row. add3 column address row address program confirm (true) command ce cle r/b we ale re i/ox 2 note : 1) tprog = program time for the last page + program time for the ( last -1) th page - (command input cycle time + address input cycle time + last page data loading time) 2) make sure to terminate the operation with 80h-10h- command sequence. if the operation is terminated by 80h-15h command sequ ence, monitor i/o 6 (ready/busy) by issu- ing status read command (70h) and make sure the previous page program operation is completed. if the page program operation is completed issue ffh reset before next operation. www..net
- 46 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.23 block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2 row add3 t whr www..net
- 47 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.24 two-plane block erase operation block erase setup command1 erase confirm command ce cle r/b i/o x we ale re 60h row add1 d0h t wc row add2 row add3 60h row add1 d0h row add2 row add3 row address t wc block erase setup command2 row address 1 erase confirm command read status command d0h 70h/f1h i/o 0 busy t wb t bers i/o 0 = 0 successful erase i/o 0 = 1 error in erase t whr 1 ce cle r/b i/o x we ale re 60h row add1,2,3 i/o 0 ~ 7 r/b 60h a 9 ~ a 25 d0h t bers e.g.) address restriction for tw o-plane block erase operation d0h 70h/f1h address address row add1,2,3 page address : fixed ?low? plane address : fixed ?low? block address : block n page address : fixed ?low? plane address : fixed ?high? block address : block n www..net
- 48 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.25 read id operation note : 1) address 00h is for samsung legacy and 40h is for new jedec id information. 4.26 00h address id cycle 4.27 40h address id cycle device 1st cycle dvice code(2nd) 3rd cycle 4th cycle 5th cycle 6th cycle k9gbg08u0a ech d7h 94h 76h 64h 43h k9lcg08u1a K9HDG08U5A device 1st cycle dvice code(2nd) 3rd cycle 4th cycle 5th cycle 6th cycle k9gbg08u0a 4ah 45h 44h 45h 43h 01h k9lcg08u1a K9HDG08U5A ce cle we ale re 90h read id command maker code device code 00h/40h ech t rea address 1cycle i/ox t ar device 4th cyc. code 3rd cyc. 5th cyc. 6th cyc. www..net
- 49 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 4.27.1 id definition table 3rd id data 4th id data description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte 6 th byte maker code device code internal chip number, cell type, number of simultaneously programmed pages, etc. page size, block size, redundant area size. plane number, ecc level, organization. device technology, edo, interface. description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 2kb 4kb 8kb reserved 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 128kb 256kb 512kb 1mb reserved reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 redundant area size ( byte / page size) reserved 128b 218b 400b 436b 640b reserved reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 www..net
- 50 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5th id data 6th id data 40h address id definition table description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 ecc level 1bit / 512b 2bit / 512b 4bit / 512b 8bit / 512b 16bit / 512b 24bit / 1kb 40bit/ 1kb reserved 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 device version 50nm 40nm 30nm 20nm reserved reserved reserved reserved 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 edo not support support 0 1 interface conventional toggle mode 0 1 reserved 0 0 0 byte description idq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 0 j 0 1 0 0 1 0 1 0 1 e 0 1 0 0 0 1 0 1 2 d 0 1 0 0 0 1 0 0 3 e 0 1 0 0 0 1 0 1 4 c 0 1 0 0 0 0 1 1 5 legacy asynchronous sdr toggle mode ddr synchronous ddr 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 www..net
- 51 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.0 device operation 5.1 page read page read is initiated by writing 00h-30h to the command register along with five address cycles. the 8,832 bytes of data with in the selected page are transferred to the cache registers via data registers in less t han tr. the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the cache register s, they may be read out in read cycle time(trc) by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the cons ecutive sequential data by writing random data output command. t he column address of next data, which is going to be out, may be changed to the addr ess which follows random data output command. random data out put can be operated multiple times regardless of how many times it is done in a page. read operation address(5cycle) 00h col. add.1,2 & row add.1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox www..net
- 52 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 random data output in a page 5.2 cache read cache read is an extension of page read, which is executed with 8,832byte data regist ers, and is available only within a block. since the device has 1 page of cache memory, serial data output may be executed while data in the memory cell is read into data registers. cache read is also initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h command is latched. therefore only five address cycles and 30h command initiates that operation after initial power up. the 8,832 bytes of data wit hin the selected page are transferred to the cache registers via data registers in less than tr. after issuing cache read command(31h), read data in the data registers is transferred to cache registers for a short period of time(t dcbsyr ). while the data in the cache registers is read out in read cycle time(trc) by sequentially pulsing re, data of next page is transferred to the data registers. by is suing last cache read command(3fh), last data is transferred to th e cache registers from the data registers after the completion of trans fer from memory cell to data registers. address 00h data output r/b re t r 30h/35h address 05h e0h 5cycles 2cycles data output data field spare field data field spare field i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 www..net
- 53 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 cache read the device has a read operation with cache registers that enables the high speed read operation s hown below. when the block add ress changes, this sequence has to be started from the beginning. note : -. if the 31h command is issued to the device, the data content of the next page is transferred to the data registers during se rial data out from the cache registers, and therefore the tr (data transfer from memory cell to data register) will be reduced. 1) normal read. data is transferred from page n to cache regist ers through data registers. during this time period, the device outputs busy state for tr max. 2) after the ready/busy returns to ready, 31h command is issued a nd data is transferred to cache registers from data registers again. this data transfer takes tdcbsyr max and the completion of this time peri od can be detected by ready/busy signal. 3) data of page n+1 is transferred to data registers from cell wh ile the data of page n in cache registers can be read out by r e clock simultaneously. 4) the 31h command makes data of page n+1 transfer to cache registers from data registers after the completion of the transfer from cell to data registers. the device outputs busy state for tdcbsyr max..this busy period depends on the combination of the internal data transfer time from cell to dat a registers and the serial data out time. 5) data of page n+2 is transferred to data registers from cell while the data of page n+1 in cache registers can be read out by re clock simultaneously. 6) the 3fh command makes the data of page n+2 transfer to the ca che registers from the data registers after the completion of t ransfer from cell to data registers. the device outputs busy state for tdcbsyr max.this busy period depends on the combination of the internal data transfer time from cel l to data registers and the transfer from data registers to cache registers. 7) data of page n+2 in cache registers can be read out, but si nce the 3fh command does not transfer the data from the memory ce ll to data registers, the device can accept new command input immediately after the completion of serial data out. ce cle r/b we ale re i/ox 00h 30h 31h 31h 0 1 2 3 8831 0 1 2 3 8831 tr page row column address address column 0 page address n page address n+1 12 4 3 tdcbsyr tdcbsyr 1 3fh 0 1 2 3 8831 0 1 2 3 8831 page address n+2 5 6 7 tdcbsyr ce cle r/b we ale re i/ox 1 30h 31h & re clock page n 31h & re clock page n+1 3fh & re clock page n+2 page n page n+1 page n+2 page n page n+1 page n+2 1 1 2 3 3 4 5 5 6 7 cache register data register www..net
- 54 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.3 two-plane page read two-plane page read is an extension of page read, for a single plane with 8,832 byte data registers. since the device is equipp ed with two memory planes, activating the two sets of 8,832 byte data registers enabl es a random read of two pages. two-plane page read is initiat ed by repeating command 60h followed by three address cycles twice. in this case, only same page of same block can be selected from each plane. after read confirm command(30h) the 17,664 bytes of data within the selected two page are transferred to the cache registers vi a data registers in less than tr. the system controller can detect the completion of data transfer(tr) by monitoring the output of r/b pin. once the data is loaded into the cache registers, the data output of first plane can be read out by issuing command 00h with fi ve address cycles, com- mand 05h with two column address and finally e0h. the data outpu t of second plane can be read out using the identical command s equences. two-plane page read must be used in the block which has been programmed with two-plane page program. two-plane page read operation with two-plane random data out 60h i/o x r/b 60h 30h t r address (3 cycle) address (3 cycle) page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?high? block address : block n column address : valid www..net
- 55 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.4 two-plane cache read two-plane cache read is an extension of cache read, for a sing le plane with 8,832 byte data regi sters. since the device is equi pped with two memory planes, activating the two sets of 8,832 byte data registers enabl es a cache read of two pages. two-plane cache read is initiat ed by repeating command 60h followed by three address cycles twice. in this case only same page of same block can be selected from each plane. after read confirm command(33h) the 17,664 bytes of data within the selected two page are transferred to the cache registers vi a data registers in less than tr. after issuing cache read command(31h), read data in the dat a registers is transferred to cache registers for a short p eriod of time(tdcbsyr). once the data is loaded into the cache registers from data regist ers, the data output of first plane can be read out by issuing command 00h with five address cycles, command 05h with two column address and finally e0h. the data output of second plane can be read out using the identical command sequences. the detail sequence of two- plane cache read is shown below. two-plane cache read operation with two-plane random data out 60h i/o x r/b 60h 33h t r address (3 cycle) address (3 cycle) page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?high? block address : block n column address : valid 31h t dcbsyr r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 3 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m + n plane address : fixed ?low? block address : block n column address : valid 4 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 4 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m + n plane address : fixed ?high? block address : block n column address : valid 3fh 3 t dcbsyr max. 127 repeatable max. 127 repeatable www..net
- 56 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.5 page program the device is programmed basical ly on a page basis, and the number of consecutiv e partial page programming operation within the same page without an intervening erase operation(nop) must not exceed 1 time for the page, and partial programming less than the minimum randomiz ation unit is not allowed. also, unwritten sectors in a page must be loaded with r andomized data before program operation. the addressing should be done in sequential order in a block. a page program cycle c onsists of a serial data loading period in which up to 8,832bytes of data may be loaded into the data registers via cache registers, followed by a non-volatile programming peri od where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command(80h) , followed by the fi ve cycle address input s and then serial data loading. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). random da ta input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming pr ocess. writing 10h alone without previously entering the seri al data will not initiate the programming process. the internal write state controller aut omatically executes the algorit hms and timings necessary for pr ogram and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status reg- ister. the system controller can detect the comp letion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programmi ng is in progress. when the page program is complete, the wr ite status bit(i/ o 0) may be checked. the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the c ommand register remains in read status command mode until another valid command is written to the command register. program & read status operation random data input in a page 80h r/b address & data input i/o0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2,3 "0" "1" 80h r/b address & data input i/o0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2,3 col. add.1,2 data data "0" "1" www..net
- 57 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.6 copy-back program copy-back program with read for copy-back is configured to quick ly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. since the ti me-consuming re-loading cycles are removed, the system performance is improved. the be nefit is especially obvi- ous when a portion of a block is updated and the rest of the bloc k also needs to be copied to the newly assigned free block. co py-back operation is a sequential execution of read for copy-back and of copy-back program with the destination page address. a read operation with "3 5h" command and the address of the source page moves the whole 8,832byte data into the internal data buffer. a bit error is checked by sequential r eading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back pr ogram operation is initiated b y issuing page-copy data- input command (85h) with destination page address. actual progra mming operation begins after prog ram confirm command (10h) is i ssued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system controlle r can detect the com- pletion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status r egister. when the copy-back program is complete, the write status bit(i/o 0) may be checked. the command register remains in read status command mode until another valid command i s written to the command register. during copy-back program, data modifica tion is possible using random data i nput command (85h) as shown below. page copy-back program operation note : 1) copy-back program operat ion is allowed only within the same memory plane. page copy-back program operation with random data input "0" "1" 00h r/b add.(5cycles) i/o0 pass fail t prog t r source address destination address i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 35h data output 85h add.(5cycles) 10h 70h r/b source address destination address there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 col. add.1,2 00h add.(5cycles) 35h t r data output 85h add.(5cycles) data 85h add.(2cycles) data 10h t prog 70h www..net
- 58 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.7 intelligent copy-back program intelligent page copy-back program operation note : 1) intelligent copy-back progr am operation is allowed only within the same memory plane. 00h r/b add.(5cycles) t prog t r source address 1 i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 30h data output 00h add.(5cycles) 3ah t dcbsyr2 destination address col. add.1,2 & row add.1,2,3 8ch add.(5cycles) 15h data input t cbsy2 r/b i/ox col. add.1,2 & row add.1,2,3 data output 00h add.(5cycles) 3ah t dcbsyr2 destination address col. add.1,2 & row add.1,2,3 8ch add.(5cycles) 15h data input t cbsy2 data output r/b i/ox destination address col. add.1,2 & row add.1,2,3 8ch add.(5cycles) 10h data input source address 2 source address 3 source address 1 source address 2 source address n www..net
- 59 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.8 cache program cache program is an extension of page progr am, which is executed with 8,832byte data r egisters, and is avai lable only within a block. since the device has 1 page of cache memory, serial data input may be executed while data stored in data registers are programmed into memory ce ll. after writing the first set of data up to 8,832byte into the selected cache registers, cache program command (15h) instead of a ctual page program (10h) is inputted to make cache registers free and to start internal program operation. to transfer data from cache registers to data registers, the device remains in busy state for a short period of time(tcbsy) and has its cac he registers ready for the next dat a-input while the internal pr ogramming gets started with the data loaded into data registers. read status command (70h) ma y be issued to find out when cache registers become ready by p olling the cache-busy status bit(i/o 6). pass/fail status of onl y the previous page is available upon the re turn to ready state. when the next set of data is inputted with the cache program command, tcbsy is affected by the progress of pendi ng internal programming. the pr ogramming of the cache register s is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. the status bit(i/o5) for inter- nal ready/busy may be polled to identify the co mpletion of internal programming. if the system monitors the progress of program ming only with r/b , the last page of the target programming sequence must be programmed with actual page program command (10h). cache program(1/2) note : 1) cache program operation is available only within a block. 2) since programming the last page does not employ caching, the program time has to be that of page program. however, if the pr evious program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. tprog = program time for the last page + program time for the ( last -1) th page - (program command cycle time + last page data loading time) maximum tprog is 10ms in this case. 80h r/b 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h t cbsy t cbsy t cbsy t prog* 2 70h address & data input* 15h col. add1,2 & row add1,2,3 col. add1,2 & row add1,2,3 col. add1,2 & row add1,2,3 data data data col. add1,2 & row add1,2,3 data i/ox www..net
- 60 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 cache program(2/2) note : - issuing the 15h command to the device after serial data input initiates the program operation with cache registers. 1) data for page k is input to cache registers. 2) data is transferred to the data registers by the 15h command. during the transfer the ready/busy outputs busy state (tcbsy). 3) data for page k+1 is input to cache registers while the data of the page k is being programmed. 4) the programming with cache registers is terminated by the 10h command . when the device becomes ready, it shows that the int ernal programming of the page k+1 is completed. tprog* = program time for the last page + program time for the ( last -1) th page - (command input cycle time + address input cycle time + last page data loading time) maximum tprog is 10ms in this case. ce cle r/b we ale re 80h din n din 15h m max. 127 times repeatable last page input & program 80h i/ox 1 2 tcbsy last page input & program din n din 10h i/o 70h m 3 4 tprog* ce cle r/b we ale re i/ox 1 15h page k cache register data register page k page k page k+1 page k page k page k+1 page k+1 page k 1 2 3 3 4 4 10h add1 add2 add3 add4 add5 add1 add2 add3 add4 add5 1 add2 add3 add4 add5 www..net
- 61 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 pass/fail status for each page programmed by the cache progr am operation can be detected by the read status operation. ? i/o 0 : pass/fail of the current page program operation. ? i/o 1 : pass/fail of the previous page program operation. the pass/fail status on i/o 0 and i/o 1 are valid under the following conditions. ? status on i/o 0 : true ready/busy is ready state. the true ready/busy is output on i/o 5 by read status operation or r/b pin after the 10h command. ? status on i/o 1 :cache read/busy is ready state. the cache ready/busy is output on i/o 6 by read status operation or r/b pin after the 15h command. 70h 80h....15h status out 80h....15h 70h status out 70h status out 80h....15h i/o1 => invalid page1 page1 i/o0 => invalid invalid page2 page 1 page 2 page n-1 page 1 page 2 1 r/b pin true ready/busy cache ready/busy 80h....15h 70h status out 80h....10h 70h status out 70h status out page n-1 page n page n-1 page n invalid page n-2 invalid invalid page n-1 page n r/b pin true ready/busy cache ready/busy during both true ready/busy and cache ready/busy return to ready state, the pass/fail for previous page and current page can be shown through i/o 1 and i/o 0 concurrently. i/o1 => i/o0 => 1 www..net
- 62 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.9 register read out mode 1 at program operation, loaded data to the register can be read out before program confirm comm and(10h). the sequence is as follo w. register read out note : register read out operation is prohibited during cache program operation. 5.10 register read out mode 2 if program operation ended in fail, programmed data in fail can be read out from the register. the sequence is as follow. register read out note : register read out operation is prohibited during cache program operation. 80h r/b address & data input 00h e0h i/ox col add1,2 & row add1,2,3 address col add1,2 & row add1,2,3 05h address col add1,2 data output date tcwaw 80h r/b address & data input 10h i/ox col add1,2 & row add1,2,3 data 70h i/o0 fail "1" r/b 00h e0h i/ox address col add1,2 & row add1,2,3 05h address col add1,2 data output 1 1 80h r/b address & data input 10h i/ox col add1,2 & row add1,2,3 data 70h i/o0 fail "1" r/b 00h e0h i/ox address col add1,2 & row add1,2,3 05h address col add1,2 data output 1 1 tprog www..net
- 63 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.11 two-plane register read out mode 1 at two-plane program operation, loaded data to the register can be read out before program confirm command(10h). the sequence i s as follow. two-plane register read out mode 1 note : 1) it is noticeable that physically same row address is applied to two planes . 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. 3) register read out operation is prohibited during cache program operation. column address : valid page address : page m plane address : fixed ?low? block address : block n column address : valid page address : page m plane address : fixed ?high? block address : block n 80h i/o x r/b address & data input 11h 81h address & data input note* 2 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?high? block address : block n column address : valid 1 2 tdbsy tcwaw www..net
- 64 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.12 two-plane register read out mode 2 if two-plane program operation ended in fail, programmed data in fail can be read out from the register. the sequence is as fol low. two-plane register read out mode 2 note : 1) it is noticeable that physically same row address is applied to two planes . 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. 3) register read out operation is prohibited during cache program operation. column address : valid page address : page m plane address : fixed ?low? block address : block n column address : valid page address : page m plane address : fixed ?high? block address : block n 80h i/o x r/b address & data input 11h 81h address & data input note* 2 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?high? block address : block n column address : valid 1 2 10h 70h i/o0 fail "1" tdbsy tprog www..net
- 65 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.13 two-plane page program two-plane page program is an extension of page program, for a si ngle plane with 8,832 byte data r egisters. since the device is equipped with two mem- ory planes, activating the two sets of 8,832 byte data registers enables a simultaneous programming of two pages. after writing the first set of data up to 8,832 byte into the selected data registers via cache registers, dummy page program c ommand (11h) instead of actual page program command (10h) is inputted to finish data-l oading of the first plane. since no programming process is involv ed, r/b remains in busy state for a short period of time(tdbsy). read status command (70h) may be issued to find out when the device returns to ready s tate by polling the ready/busy status bit(i/o 6). then the next set of data for the other plane is inputted after the 81h command and address seque nces. after inputting data for the last plane, actual true page program(10h) instead of dummy page program command (11h) must be followed to start the pro gramming process. the operation of r/b and read status is the same as that of page program. alth ough two planes are programmed simultaneously, pass/fail is not avail - able for each page when the program operation completes. status bit of i/o 0 is set to "1" when any of the pages fails. restriction in addressing with two- plane page program is shown below. two-plane page program note : 1) it is noticeable that same row address except for the plane address is ap plied to the two blocks 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. column address : valid page address : page m plane address : fixed ?low? block address : block n column address : valid page address : page m plane address : fixed ?high? block address : block n note* 2 80h i/o 0 ~ 7 r/b address & data input 11h 81h 10h t dbsy t prog address & data input pass 70h/f1h i/o0 fail "0" "1" 80h 11h data input plane 0 (2076 block) block 0 block 2 block 4150 block 4148 81h 10h plane 1 (2076 block) block 1 block 3 block 4151 block 4149 www..net
- 66 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.14 two-plane copy-back program two-plane copy-back program is an extensio n of copy-back program, for a single plane wi th 8,832 byte data registers. since the device is equipped with two memory planes, activating the two sets of 8,832 by te data registers enables a simu ltaneous programming of two pages. two-plane copy-back program operation r/b 85h 70h/f1h t prog add.(5cycles) destination address 10h i/ox col. add.1,2 & row add.1,2,3 81h add.(5cycles) destination address col. add.1,2 & row add.1,2,3 11h t dbsy 3 note2 60h i/o x r/b 60h 35h t r address (3 cycle) address (3 cycle) 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row add.1,2,3 col. add.1,2 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row add.1,2,3 col. add.1,2 3 page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n column address: fixed "low" page address : page m plane address : fixed ?low? block address : block n column address: valid column address: fixed "low" page address : page m plane address : fixed ?high? block address : block n column address: valid column address: fixed "low" page address : page m plane address : fixed ?low? block address : block n column address: fixed "low" page address : page m plane address : fixed ?high? block address : block n www..net
- 67 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 note : 1) copy-back program operation is allowed only within the same memory plane. 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. data field spare field (1) (3) plane0 source page target page (1) : two-plane read for copy back (2) : two-plane random data out (3) : two-plane copy-back program (2) data field spare field (1) (3) plane1 source page target page (2) www..net
- 68 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 two-plane copy-back program operation with random data input note : 1) copy-back program operation is allowed only within the same memory plane. 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. r/b 85h 11h t dbsy add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) r/b 81h 10h t prog add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 3 4 4 destination address destination address note2 60h i/o x r/b 60h 35h t r address (3 cycle) address (3 cycle) 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row add.1,2,3 col. add.1,2 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row add.1,2,3 col. add.1,2 3 page address : fixed ?low? plane address : fixed ?low? block address : block n page address : valid plane address : fixed ?high? block address : block n column address: fixed "low" page address : page m plane address : fixed ?low? block address : block n column address: valid column address: valid column address: fixed "low" page address : page m plane address : fixed ?high? block address : block n column address: valid page address : page m plane address : fixed ?low? block address : block n column address: valid column address: valid page address : page m plane address : fixed ?high? block address : block n column address: valid www..net
- 69 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.15 two-plane intelligent copy-back program(1/2) two-plane intelligent copy-back program operation r/b 8ch t cbsy2 add.(5cycles) destination address 15h i/ox col. add.1,2 & row add.1,2,3 8ch add.(5cycles) destination address col. add.1,2 & row add.1,2,3 11h t dbsy 4 note2 60h i/o x r/b 60h 30h t r address (3 cycle) address (3 cycle) 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row add.1,2,3 col. add.1,2 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row add.1,2,3 col. add.1,2 3 page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n column address: fixed "low" page address : page m plane address : fixed ?low? block address : block n column address: valid column address: fixed "low" page address : page m plane address : fixed ?high? block address : block n column address: valid column address: fixed "low" page address : page n plane address : fixed ?low? block address : block n column address: fixed "low" page address : page n plane address : fixed ?high? block address : block n 60h i/o x r/b 60h 3ah t dcbsyr2 address (3 cycle) address (3 cycle) row add.1,2,3 row add.1,2,3 page address : page m+1 plane address : fixed ?low? block address : block n page address : page m+1 plane address : fixed ?high? block address : block n 3 4 data input data input 5 www..net
- 70 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 two-plane intelligent copy-back program(2/2) note : 1) two-plane intelligent copy-back program operation is allowed only within the same memory plane. 2) any command between 11h and 8ch is prohibited except 70h/f1h and ffh. r/b 8ch t prog add.(5cycles) destination address 10h i/ox col. add.1,2 & row add.1,2,3 8ch add.(5cycles) destination address col. add.1,2 & row add.1,2,3 11h t dbsy 7 note2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 5 col. add. 1,2 & row add.1,2,3 col. add.1,2 6 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 6 col. add. 1,2 & row add.1,2,3 col. add.1,2 7 column address: fixed "low" page address : page m+1 plane address : fixed ?low? block address : block n column address: valid column address: fixed "low" page address : page m+1 plane address : fixed ?high? block address : block n column address: valid column address: fixed "low" page address : page n+1(final) plane address : fixed ?low? block address : block n column address: fixed "low" page address : page n+1(final) plane address : fixed ?high? block address : block n data input data input www..net
- 71 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 pass/fail status for each page programmed by the intelligent c opy-back program operation can be detected by the read status ope ration. ? i/o 0 : pass/fail of the current page program operation. ? i/o 1 : pass/fail of the previous page program operation. the pass/fail status on i/o 0 and i/o 1 are valid under the following conditions. ? status on i/o 0 : true ready/busy is ready state. the true ready/busy is output on i/o 5 by read status operation or r/b pin after the 10h command. ? status on i/o 1 :cache read/busy is ready state. the cache ready/busy is output on i/o 6 by read status operation or r/b pin after the 15h command. 70h 00h....3ah status out 8ch....15h i/o1 => invalid invalid i/o0 => invalid valid page n r/b pin true ready/busy cache ready/busy 00h....3ah 70h status out 00h....3ah 70h status out invalid invalid valid invalid r/b pin true ready/busy cache ready/busy i/o1 => i/o0 => 70h status out read for copy-back page n - 1 copy-back program case 2 page n read for copy-back page n - 1 copy-back program 8ch....15h page n + 1 read for copy-back case 1 www..net
- 72 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.16 two-plane cache program two-plane cache program is an extension of cache program, for a single plane with 8,832 byte data registers. since the device i s equipped with two memory planes, activating the two sets of 8,832 byte data r egisters enables a simultaneous programming of two pages. two-plane cache program operation note : 1) it is noticeable that same row address except for a20 is applied to the two blocks 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. 3) since programming the last page does not employ caching, the program time has to be that of page program. however, if the pr evious program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after co mpletion of the prev ious cycle, which can be expressed as the following formula. tprog = program time for the last page + program time for the ( last -1) th page - (program command cycle time + last page data loading time) i/o x r/b 1 r/b i/ox 1 column address : valid page address : page m plane address : fixed ?low? block address : block n column address : valid page address : page m plane address : fixed ?high? block address : block n 80h address & data input 11h 81h 15h address & data input column address : valid page address : page m+n plane address : fixed ?low? block address : block n column address : valid page address : page m+n plane address : fixed ?high? block address : block n 80h address & data input 11h 81h 10h address & data input t dbsy t dbsy t prog t cbsy max. 127 times repeatable 80h 11h cache register plane 0 (2076 block) block 0 block 2 block 4150 block 4148 81h 15h plane 1 (2076 block) block 1 block 3 block 4151 block 4149 data register 1 2 3 1 2 3 3 www..net
- 73 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.17 block erase the erase operation is done on a block basis. block address loading is acco mplished in three cycles initiated by an erase setup command(60h). only plane address and block address are valid whil e page address is ignored. the erase conf irm command(d0h) following the block add ress loading initi- ates the internal erasing process. this two-step sequence of setup followed by executi on command ensures that memory contents a re not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write cont roller handles erase and erase- verify. when the erase operation is completed, the write status bit(i/o 0) may be checked. block erase operation 5.18 two-plane block erase basic concept of two-plane block erase operat ion is identical to that of two-plane p age program. up to two blocks, one from eac h plane can be simul- taneously erased. standard block erase comm and sequences (block erase setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. on ly one block should be selected from each pl ane. the erase confirm command(d0h) initia tes the actual erasing process. the completion is detected by monitoring r/b pin or ready/busy status bit (i/o 6). two-plane block erase operation 60h row add 1,2,3 r/b address input(3cycle) i/o0 pass d0h 70h t bers i/ox "0" "1" fail 60h i/o x r/b 60h d0h i/o0 pass fail t bers address (3 cycle) address (3 cycle) 70h/f1h "0" "1" page address : fixed ?low? plane address : fixed ?low? block address : block n page address : fixed ?low? plane address : fixed ?high? block address : block n row add 1,2,3 row add 1,2,3 www..net
- 74 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.19 read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. after writing 70h or f1h command to the command register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows t he system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated stat us. refer to the table for specific 70h status register definitions and f1h status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. status register definition for 70h command note : 1) i/os defined ?not use? are recommended to be masked out when read st atus is being executed. 2) n : current page, n-1: previous page. status register definition for f1h command note : 1) i/os defined ?not use? are recommended to be masked out when read st atus is being executed. 2) n : current page, n-1 : previous page. i/o page program block erase cache program intelligent copy-back program read cache read intelligent copy-back read definition i/o 0 pass/fail pass/fail pass/fail(n) pas s/fail(n) not use not use not use pass : "0" fail : "1" i/o 1 not use not use pass/fail(n-1) pass/fail(n-1) not use not use not use pass : "0" fail : "1" i/o 2 not use not use not use not use not use not use not use don?t -cared i/o 3 not use not use not use not use not use not use not use don?t -cared i/o 4 not use not use not use not use not use not use not use don?t -cared i/o 5 not use not use true ready/busy true ready/busy not use true ready/busy true ready/busy busy : "0" ready : "1" i/o 6 ready/busy ready/busy cache ready/busy cache ready/busy ready/busy cache ready/ busy cache ready/ busy busy : "0" ready : "1" i/o 7 write protect write protect write protect write protect write protect write protect write protect protected : "0" not protected : "1" i/o page program block erase cache program intelligent copy-back program read cache read intelligent copy-back read definition i/o 0 chip pass/fail chip pass/fail chip pass/fail(n) chip pass/fail(n) not use not use not use pass : "0" fail : "1" i/o 1 plane0 pass/fail plane0 pass/fail plane0 pass/fail(n) plane0 pass/fail(n) not use not use not use pass : "0" fail : "1" i/o 2 plane1 pass/fail plane1 pass/fail plane1 pass/fail(n) plane1 pass/fail(n) not use not use not use pass : "0" fail : "1" i/o 3 not use not use plane0 pass/fail(n-1) plane0 pass/fail(n-1) not use not use not use pass : "0" fail : "1" i/o 4 not use not use plane1 pass/fail(n-1) plane1 pass/fail(n-1) not use not use not use pass : "0" fail : "1" i/o 5 not use not use true ready/busy true ready/busy not use true ready/busy true ready/busy busy : "0" ready : "1" i/o 6 ready/busy ready/busy cache ready/busy cache ready/busy ready/busy cache ready/busy cache ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect write protect write protect write protect write protect protected : "0" not protected : "1" www..net
- 75 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.20 read id the device contains a product ident ification mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. six read cycles sequentially output the manufacturer code(ech), and the device c ode and 3rd, 4th, 5th, 6th cycle id respectively. the command register remains in read id mode until further commands are issued to it. read id operation 5.21 reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait fo r the next command, and the status register is cleared to value c0h when wp is high. refer to table for device status after reset operation. if the dev ice is already in reset state a new reset command will be acc epted by the command regis- ter. the r/b pin changes to low for trst after the reset command is written. reset operation device status device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle 6th cycle k9gbg08u0a d7h 94h 76h 64h 43h k9lcg08u1a K9HDG08U5A after power-up after reset operation mode mode 00h command is latched waiting for next command ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea t whr t clr device 4th cyc. code ech 3rd cyc. 5th cyc. 6th cyc. ffh i/o x r/b t rst www..net
- 76 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.22 output driver setting the device supports four kinds of output driver setting for matchi ng the system characteristics. the nominal output drive stren gth is the power-on default value. the host is able to select a different drive strength setting using the set features (efh) command with following 10h ad dress (driver setting feature address). the output impedance range from minimum to maximu m covers process, voltage, and temperature variations. devic es are not guaran- teed to be at the nominal value. the users can tune the output driver impedance of the data by setting the driver strength regi ster value. (see configura- tion register table) table 5 shows which output driver would be tuned and the strength according to setting data. upon power-up , the register will revert to the default setting. table 6 & table 7 shows the output driver strength impedance values of each strength and pull-up and pu ll down output impedance mismatch. driver strength register setting note : 1) b0-b3 are parameters identifying new settings for the feature specified. table 5. output driver setting b0 value driver strength 00h~01h reserved 02h driver multiplier : underdriver1 03h reserved 04h driver multiplier : 1 (default) 05h reserved 06h driver multiplier :overdriver1 07h reserved 09h reserved 0ah ~ffh reserved r/b tfeat ce cle ale we efh 10h re b0 b1 b2 b3 (1) efh i/ox tadl twc twb www..net
- 77 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 driver strength register getting table 6. output drive strength impedance values table 7. pull-up and pull-down output impedance mismatch note : 1) mismatch is the absolute value between pull-up and pull-down im pedances. both are measured at the same temperature and volta ge. 2) test conditions: vccq = vccq(min), vout = vccq 0.5, t a = t oper output strength rpd/rpu vout to vssq minimum nominal maximum units vccq(3.3v) vccq(3.3v) vccq(3.3v) overdrive1 rpd vccq 0.2182743ohms vccq 0.5203253ohms vccq 0.8294677ohms rpu vccq 0.2294677ohms vccq 0.5203253ohms vccq 0.8182743ohms nominal rpd vccq 0.2233454ohms vccq 0.5264068ohms vccq 0.8365796ohms rpu vccq 0.2365796ohms vccq 0.5264068ohms vccq 0.8233454ohms underdrive rpd vccq 0.2304572ohms vccq 0.5345391ohms vccq 0.8 48 76 128 ohms rpu vccq 0.2 48 76 128 ohms vccq 0.5345391ohms vccq 0.8304572ohms drive strength min max unit notes vccq(3.3v) vccq(3.3v) overdrive 1 0 8 ohms 1, 2 nominal 0 10 ohms 1, 2 underdrive 0 14 ohms 1, 2 ce cle ale we efh 10h re b0 b1 b2 (1) eeh i/ox r/b tfeat b3 www..net
- 78 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.23 ready/ busy the device has a r/b output that provides a hardware method of indicating the comp letion of a page program, erase and random read completion. the r / b pin is normally high but transit ions to low after program or erase command is written to the command register or random read i s started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby al lowing two or more r/b outputs to be or-tied. because pull-up resi stor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the fol- lowing reference chart. its value c an be determined by the following guidance. rp value guidance where i l is the sum of the input currents of all devices tied to the r/b pin. rp(max) is determined by maxi mum permissible limit of tr v cc r/b open drain output device gnd rp ibusy c l busy ready vcc voh tf tr vol 3.3v device - v ol : 0.4v, v oh : 2.4v rp vs tr ,tf & rp vs ibusy tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 50pf 1k 2k 3k 4k 100n 200n 2m 1m 50 tf 100 150 200 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 rp(min, 3.3v part) = vcc(max.) - vol(max.) iol + il = 3.2v 8ma + i l www..net
- 79 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 5.24 00h address id cycle 5.25 40h address id cycle 5.26 device identification table read operation the device supports the device id table read operation to give mo re id information such as the device?s organization, features, timings and other param- eters. refer to the device id table read timing diagram below. values in the device id table are static and shall not change. device id table read device 1st cycle dvice code(2nd) 3rd cycle 4th cycle 5th cycle 6th cycle k9gbg08u0a ech d7h 94h 76h 64h 43h k9lcg08u1a K9HDG08U5A device 1st cycle dvice code(2nd) 3rd cycle 4th cycle 5th cycle 6th cycle k9gbg08u0a 4ah 45h 44h 45h 43h 01h k9lcg08u1a K9HDG08U5A ech value of device id table ce cle ale r/b we re t r 40h i/ox www..net
- 80 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 device id table definitions note : values in the device id table are tbd byte o/m description value revision information and features block 0-3 m parameter page signature byte 0: ?j? (= 4ah) byte 1: ?e? (= 45h) byte 2: ?s? (= 53h) byte 3: ?d? (= 44h) 4ah, 45h, 53h, 44h 4-5 m revision number 2-15: reserved (0) 1: 1 = supports revision 1.0 0: reserved (0) 02h, 00h 6-7 m features supported 0-15 reserved (0) tbd 8-10 m optional commands supported 0-23: reserved (0) tbd 11-3111-31 reserved (0) all 00h manufacturer information block 32-43 m device manufacturer (12 ascii characters) 53h, 41h, 4dh, 53h 55h, 4eh, 47h, 20h 20h, 20h, 20h, 20h 44-63 m device model (20 ascii characters) 4bh, 39h, 36h, 41h, 47h 44h, 38h, 55h, 30h, 4dh 20h, 20h, 20h, 20h, 20h 20h, 20h, 20h, 20h, 20h 64-69 m jedec manufacturer id (6 bytes) ech, 00h, 00h,00h,00h,00h 70-71 tbd tbd tbd 72-79 reserved (0) memory organization block 80-83 m number of data bytes per page 00h, 20h, 00h, 00h 84-85 m number of spare bytes per page 00h, 02h 86-89 m tbd tbd 90-91 m tbd tbd 92-95 m number of pages per block 40h, 00h, 00h, 00h 96-99 m number of blocks per logical unit 38h, 10h, 00h, 00h 100 m number of logical unit 01h 101-255 tbd tbd tbd redundant parameter pages 255-511 m redundant parameter pages value of byte 0-255 512-767 m redundant parameter pages value of byte 0-255 from768 o additional redundant parameter pages. tbd www..net
- 81 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 6.0 data protection & power up sequence the device is designed to offer pr otection from any involuntary program/erase du ring power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 2v. the reset command(ffh) must be issued to all ce s as the first command after the nand flash device is powered on. each ce will be busy for a maximum of 5ms after a reset command is is sued. in this time period, the acceptable command is 70h/f1h. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. the two step command sequence for pro- gram/erase provides additional software protection. ac waveforms for power transition note : 1) during the initialization, the device consumes a maximum current of 50ma (icc1) 2) vcc should be reached the valid voltage no later than vccq. v cc/ v cc q (2) wp high we r/b 100 s vcc : ~ 2.7v invalid don?t care don?t care cle ce i/ox ffh 5ms max don?t care operation 100 s vccq : (3.3v) : ~2.7v vccq : (3.3v) : ~2.7v vcc : ~ 2.7v www..net
- 82 - datasheet k9gbg08u0a k9lcg08u1a K9HDG08U5A flash memory rev. 1.0 6.1 wp ac timing guide enabling wp during erase and program busy is prohibited. the eras e and program operations are enabled and disabled as follows: program operation 1. enable mode 2. disable mode erase operation 1. enable mode 2. disable mode 80h 10h we i/o wp r/b tww(min.100ns) 80h 10h tww(min.100ns) we i/o wp r/b 60h d0h tww(min.100ns) we i/o wp r/b 60h d0h tww(min.100ns) we i/o wp r/b www..net

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